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<title>PM0044 5.4.3 Pipeline with Call/Jump, table 10</title>
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    .pipetrace td.Sbus:before { content: " S₀"; }
    .pipetrace td.Sfetch:before { content: " S₁"; }
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<h1>PM0044 5.4.3 Pipeline with Call/Jump, table 10</h1>

<table id="pipetrace_legend" class="pipetrace">
    <tr><td colspan="2">Legend</td></tr>
    <tr><td class="D" /><td class="defn">Decode</td></tr>
    <tr><td class="E" /><td class="defn">Execute</td></tr>
    <tr><td><span class="F" /></td><td class="defn">Fetch</td></tr>
    <tr><td class="X" /><td class="defn">Flush</td></tr>
    <tr><td><span class="FS" /></td><td class="defn">Fetch Stall - space in prefetch buffer but bus busy</td></tr>
    <tr><td class="Sbus" /><td class="defn">Decode Stall - bus busy</td></tr>
    <tr><td class="Sfetch" /><td class="defn">Decode Stall - insufficient data in prefetch buffer</td></tr>
    <tr><td class="Sraw" /><td class="defn">Decode Stall - read after write</td></tr>
</table>

<p>PM0044 table 10 shows a fetch stall in the first execution cycle
of the call (cycle 7) however it should be possible for a fetch
to take place since pushing the return address only busies the
data bus (and STM8 is a Harvard architecture with unified address
space so the data and program are separate buses).</p>
<p>Also note that since the flush happens on the last execute cycle
of the call (unlike the jp) there is no overlap and we mark
the following cycle as a decode stall. Technically this is correct
but table 10 does not and says the call takes 3 cycles which
ignores the unavoidable stall cycle. The later instruction documentation
for call says it takes 4 cycles which is presumed to include the
stall cycle that follows it.</p>
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        <tr><td /><td class="Flushed" /></tr>
        <tr><td>0x080c4</td><td class="instr">inc    A</td><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
        <tr><td>0x080c5</td><td class="instr">jp     0x80cc</td><td class="" /><td class="" /><td class=" D X"></td><td class=" E" /></tr>
        <tr><td /><td class="Flushed" /></tr>
        <tr><td>0x080cc</td><td class="instr">neg    A</td><td class="" /><td class="" /><td class="" /><td class=""><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
        <tr><td>0x080cd</td><td class="instr">call   0x80d8</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=" D"><span class="F" /></td><td class=" E"><span class="F" /></td><td class=" E X" /></tr>
        <tr><td /><td class="Flushed" /></tr>
        <tr><td>0x080d8</td><td class="instr">incw   X</td><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class="" /><td class=""></td><td class=" D Sfetch"><span class="F" /></td><td class=" D"><span class="F" /></td><td class=" E" /></tr>
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        <tr><th>Address</th><th>Instruction</th><th class="n">1</th><th class="n">2</th><th class="n">3</th><th class="n">4</th><th class="n">5</th><th class="n">6</th><th class="n">7</th><th class="n">8</th><th class="n">9</th><th class="n">10</th><th class="n">11</th>
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